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? 2008 omnivision technologies, inc. variopixel, omnivision, and t he omnivision logo are registered trademarks of omnivision tec hnologies, inc. version 1.1, october 10, 2007 camerachip and omnipixel2 are trademarks of omnivision technologies, inc. these specifications are subj ect to change without notice. advanced information datasheet OV9665 color cmos sxga (1.3 megapixel) c amera c hip tm sensor o mni ision ? with omnipixel2 tm technology general description the OV9665 c amera c hip ? image sensor is a low voltage cmos device that prov ides the full functionality of a single-chip sxga (1280x1024) camera and image processor in a small foot print package. the OV9665 provides full-frame, sub-sampled, scaled or windowed 8-bit/10-bit images in a wide range of formats, controlled through the serial camera control bus (sccb) interface. this product has an image array capable of operating at up to 15 frames per second (fps) in sxga resolution with complete user control over image quality, formatting and output data transfer. all required image processing functions, including exposure control, gamma, white balance, color saturation, hu e control, defect pixel canceling, noise canceling, and more, are also programmable through the sc cb interface. in addition, omnivision sensors use proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable color image. features ? high sensitivity for low-light operation ? low operating voltage for embedded portable applications ? standard sccb interface ? supports image sizes: sxga, vga, cif, scaled down and windowed outputs with raw rgb, rgb565/555/444, yuv (4:2:2) and ycbcr (4:2:2) formats ? variopixel ? method for sub-sampling ? automatic image cont rol functions including automatic exposure contro l (aec), automatic gain control (agc), automatic white balance (awb), and automatic black-level calibration (ablc) ? image quality controls including color saturation, hue, gamma, sharpness (edge enhancement), lens correction, defect pixel canceling, noise canceling, and 50/60 hz luminance detection ordering information pb note: the OV9665 uses a lead-free package. product package ov09665-vl9a (color, lead-free) 26-pin csp2 applications ? cellular and picture phones ?toys ? pc multimedia ? digital still cameras key specifications figure 1 OV9665 pin diagram (top view) 1 active array size 1304 x 1036 power supply analog 2.45 to 3.0vdc i/o 1.71v to 3.0v power requirements active 80 mw typical (15fps) standby 15 a typical temperature range operation -30c to 70c stable image 0c to 50c output formats (8-bit) ? yuv/ycbcr 4:2:2 ? rgb565/555/444 ? raw rgb data lens size 1/5.5" chief ray angle 25 non-linear maximum image transfer rate sxga 15 fps vga and down scaling 30 fps sensitivity 450 mv/(lux ? sec) s/n ratio 40 db dynamic range 55 db scan mode progressive maximum exposure interval 1052 x t row gamma correction programmable pixel size 2.0 m x 2.0 m dark current 3 mv/sec @ 60c well capacity 13 ke fixed pattern noise 1% of v peak-to-peak image area 2608 m x 2072 m package dimensions 4485 m x 4985 m 1 OV9665 pin diagram ? 2008 omnivision technologies, inc. a1 vrefh a2 vrefn a3 d8 OV9665 a4 d6 a5 d7 b1 agnd b2 avdd b4 d4 b5 d5 c1 pwdn c2 resetb c4 d2 c5 d3 d1 sio_c d2 sio_d d4 d0/strobe d5 d1 e1 xvclk e2 d9 e4 vrefd e5 vsync f1 dognd f2 dovdd f3 vrefd f4 pclk f5 href 9665csp_ds_001 www.datasheet.co.kr datasheet pdf - http://www..net/
2 proprietary to omnivisi on technologies, inc. version 1.1, october 10, 2007 OV9665 color cmos sxga (1.3 megapixel) omnipixel2? c amera c hip ? sensor o mni ision functional description figure 2 shows the functional block diagram of t he OV9665 image sensor. the OV9665 includes: ? image sensor array (1304 x 1036 active image array) ? analog signal processor ? a/d converters ? digital signal processor (dsp) ? output formatter ? timing generator ? sccb interface ? digital video port figure 2 functional block diagram column sense amp row select image array strobe href pclk vsync sio_c resetb pwdn clock exposure/ gain detect 50/60 hz auto detect test pattern generator video port fifo dsp* buffer buffer image scaler analog processing video timing generator dsp* (lens shading correction, de-noise, defect pixel correction, auto white balance, etc.) note 1 exposure/gain control sccb interface xvclk sio_d registers a/d a/d g r b d [9:0] 9665csp_ds_002 www.datasheet.co.kr datasheet pdf - http://www..net/
functional description version 1.1, october 10, 2007 proprietary to omnivisi on technologies, inc. 3 o mni ision image sensor array the OV9665 sensor has an active image array of 1304 columns by 1036 rows (1,350,944 pixels). figure 3 shows a cross-section of the image sensor array. figure 3 image sensor array timing generator in general, the timing generator controls the following functions: ? array control and frame generation ? internal timing signal generation and distribution ? frame rate timing ? automatic exposure control (aec) ? external timing outputs (vsync, href/hsync, and pclk) analog signal processor this block performs automa tic gain control (agc). a/d converters after the analog processing block, the bayer pattern raw signal is fed to two 10-bit analog-to-digital (a/d) converters, one for the g channel and one shared by the br channels. these a/d conv erters operate at speeds up to 27 mhz and are fully synchronous to the pixel rate (actual conversion rate is related to the frame rate). in addition to the a/d conversion, this block also has the following functions: ? digital black-level calibration (blc) ? optional u/v channel delay ? additional a/d range controls blue green microlens glass microlens microlens red 9665csp_ds_003 in general, the combination of the a/d range multiplier and a/d range control sets the a/d range and maximum value to allow the user to adjust the final image brightness as a function of the individual application. digital signal processor (dsp) this block controls the interpolation from raw data to rgb and some image quality control. ? automatic white balance (awb) ? edge enhancement (a two-dimensional high pass filter) ? color space converter (can change raw data to rgb or yuv/ycbcr) ? rgb matrix to eliminate color cross talk ? hue and saturation control ? programmable gamma control ? transfer 10-bit data to 8-bit ? defect pixel canceling ? de-noise output formatter this block controls all output and data formatting required prior to sending the image out. strobe mode the OV9665 has a strobe mode t hat allows it to work with an external flash and led. digital video port register bits com2 [1:0] increase i ol /i oh drive current and can be adjusted as a function of the customer?s loading. sccb interface the serial camera control bus (sccb) interface controls the c amera c hip sensor operation. refer to omnivision technologies serial camera control bus (sccb) specification for detailed usage of the serial control port. www.datasheet.co.kr datasheet pdf - http://www..net/
4 proprietary to omnivisi on technologies, inc. version 1.1, october 10, 2007 OV9665 color cmos sxga (1.3 megapixel) omnipixel2? c amera c hip ? sensor o mni ision pin description 1 note: d[9:2] for 8-bit yuv or rgb565/ rgb555 (d[9] msb, d[2] lsb) d[9:0] for 10-bit raw rgb data (d[9] msb, d[0] lsb) 1 OV9665 pin description list ? 2008 omnivision technologies, inc. table 1 pin description pin location name pin type function/description a1 vrefh reference internal analog voltage reference - connect to analog ground through a 0.1f capacitor a2 vrefn reference internal analog voltage reference - connect to analog ground through a 0.1f capacitor a3 d8 output video output bit[8] a4 d6 output video output bit[6] a5 d7 output video output bit[7] b1 agnd power ground for analog circuit b2 avdd power power for analog circuit b4 d4 output video output bit[4] b5 d5 output video output bit[5] c1 pwdn input power down function (active high) with internal pull-down resistor c2 resetb input reset function (active low) with internal pull-up resistor c4 d2 output video output bit[2] c5 d3 output video output bit[3] d1 sio_c input sccb serial interface clock input without internal pull-up/pull-down resistor d2 sio_d i/o sccb serial interface data i/o d4 d0/strobe output video output bit[0] when in 10-bit output mode or strobe output when in 8-bit output mode. d5 d1 output video output bit[1] e1 xvclk input system clock input without internal pull-up/pull-down resistor e2 d9 output video output bit[9] e4 vrefd reference digital reference - connect to digital ground through a 0.1f capacitor and connect with pin f3 e5 vsync output vertical sync output f1 dognd power ground for digital / video port f2 dovdd power power for digital / video port f3 vrefd reference digital reference - connect to digital ground through a 0.1f capacitor and connect to pin e4 f4 pclk output pixel clock output f5 href output horizontal reference output www.datasheet.co.kr datasheet pdf - http://www..net/
electrical characteristics version 1.1, october 10, 2007 proprietary to omnivisi on technologies, inc. 5 o mni ision electrical characteristics note: exceeding the absolute maximum ratings shown above invalidat es all ac and dc electrical specifications and may result in permanent device damage. table 2 absolute maximum ratings ambient storage temperature -40oc to +95oc supply voltages (with respect to ground) v dd-a 4.5 v v dd-io 4.5 v all input/output voltages (with respect to ground) -0.3v to v dd-io +0.5v lead-free temperature, surface-mount process 245oc table 3 dc characteristics (-30c < t a < 70c) symbol parameter condition min typ max unit v dd-a dc supply voltage ? analog ? 2.45 2.8 3.0 v v dd-io dc supply voltage ? i/o ? 1.71 1.8 3.0 v i dda active (operating) current see note a a. at 25c, v dd-a = 2.8v, v dd-io = 1.8v i dda = {i dd-a + i dd-io }, f clk = 24mhz at 15 fps ycbcr output with typical loading 17 + 18 b b. i dd-io = 17ma, i dd-a = 18ma, with typical loading 50 ma i dds-sccb standby current see note c c. at 25c, v dd-a = 2.8v, v dd-io = 1.8v i dds-sccb refers to a sccb-initiated standby, while i dds-pwdn refers to a pwdn pin-initiated standby 12ma i dds-pwdn standby current 15 30 a v ih input voltage high cmos 0.7 x v dd-io v v il input voltage low 0.3 x v dd-io v v oh output voltage high cmos 0.9 x v dd-io v v ol output voltage low 0.1 x v dd-io v www.datasheet.co.kr datasheet pdf - http://www..net/
6 proprietary to omnivisi on technologies, inc. version 1.1, october 10, 2007 OV9665 color cmos sxga (1.3 megapixel) omnipixel2? c amera c hip ? sensor o mni ision table 4 functional and ac characteristics (-30c < t a < 70c) symbol parameter min typ max unit functional characteristics a/d differential non-linearity + 1/2 lsb a/d integral non-linearity + 1lsb inputs ( pwdn , xvclk and resetb ) f clk input clock frequency with pll 102427mhz without pll 102454mhz t clk:dc clock duty cycle 45 50 55 % t s:resetb setting time after soft ware/hardware reset 1 ms t s:reg settling time for register change 300 ms sccb timing (see figure 4 ) f sio_c clock frequency 400 khz t low clock low period 1.3 s t high clock high period 600 ns t aa sio_c low to data out valid 100 900 ns t buf bus free time before new start 1.3 s t hd:sta start condition hold time 600 ns t su:sta start condition setup time 600 ns t hd:dat data in hold time 0 s t su:dat data in setup time 100 ns t su:sto stop condition setup time 600 ns t r, t f sccb rise/fall times 300 ns t dh data out hold time 50 ns outputs ( vsync , href , pclk , and d[9:0] (see figure 5 , figure 6 , and figure 7 ) t pdv pclk [ ] to data out valid 5 ns t su d[9:0] setup time 15 ns t hd d[9:0] hold time 8 ns t phh pclk [ ] to href [ ]05ns t phl pclk [ ] to href [ ]05ns ac conditions: ? v dd : v dd-a = 2.8v, v dd-io = 1.8v ? rise/fall times: i/o: 5ns, maximum sccb: 300ns, maximum ? input capacitance: 10pf ? output loading: 20pf ? f clk : 24mhz www.datasheet.co.kr datasheet pdf - http://www..net/
timing specifications version 1.1, october 10, 2007 proprietary to omnivisi on technologies, inc. 7 o mni ision timing specifications figure 4 sccb timing diagram figure 5 horizontal timing note: timing may vary depending on register settings. sio_d (out) t aa t dh sio_c t f t r t high t low t su:dat sio_d (in) t hd:dat t su:sto t su:sta t hd:sta t buf 9665csp_ds_004 d[9:0] href (row data) last byte last byte zero first byte pclk t su t hd t pclk t phh t phl t pdv 9665csp_ds_005 www.datasheet.co.kr datasheet pdf - http://www..net/
8 proprietary to omnivisi on technologies, inc. version 1.1, october 10, 2007 OV9665 color cmos sxga (1.3 megapixel) omnipixel2? c amera c hip ? sensor o mni ision figure 6 sxga frame timing figure 7 vga 30 frame timing d[9:0] href vsync note1 for raw data, t p = internal pixel clock note2 for yuv/rgb, t p = 2 x internal pixel clock note3 this timin g dia g ram is for reference only; different settin g s will result in different timin g values 1052 x t line 4 x t line 21497 t p 240 t p p0 - p1279 1280 t p row 0 invalid data row 1 row 2 row 1023 t line = 1520 t p 15223 t p 9665csp_ds_006 d[9:0] href vsync note1 for raw data, t p = internal pixel clock note2 for yuv/rgb, t p = 2 x internal pixel clock 526 x t line 18349.5 t p 3033.5 t p 120 t p p0 - p639 640 t p row 0 invalid data row 1 row 2 row 479 t line = 760 t p 13697 t p 9665csp_ds_007 note3 this timin g dia g ram is for reference onl y ; different settin g s will result in different timin g values www.datasheet.co.kr datasheet pdf - http://www..net/
timing specifications version 1.1, october 10, 2007 proprietary to omnivisi on technologies, inc. 9 o mni ision figure 8 rgb 565 output timing diagram figure 9 rgb 555 output timing diagram d[9:2] href (row data) last byte last byte zero first byte pclk t su t hd t pclk t phh t phl t pdv d[9] first byte second byte r 4 d[8] . d[7] . d[6] . d[5] r 0 d[4] g 5 d[3] . d[2] g 3 d[9] g 2 d[8] . d[7] g 0 d[6] b 4 d[5] . d[4] . d[3] . d[2] b 0 9665csp_ds_013 d[9:2] href (row data) last byte last byte zero first byte pclk t su t hd t pclk t phh t phl t pdv d[9] first byte second byte x d[8] r 4 d[7] . d[6] . d[5] . d[4] r 0 d[3] g 4 d[2] g 3 d[9] g 2 d[8] . d[7] g 0 d[6] b 4 d[5] . d[4] . d[3] . d[2] b 0 9665csp_ds_014 www.datasheet.co.kr datasheet pdf - http://www..net/
10 proprietary to omnivisi on technologies, inc. version 1.1, october 10, 2007 OV9665 color cmos sxga (1.3 megapixel) omnipixel2? c amera c hip ? sensor o mni ision figure 10 rgb 444 output timing diagram d[9] g 7 d[8] . d[7] . d[6] g 4 d[5] b 7 d[4] . d[3] . d[2] b 4 d[9] 0 d[8] . d[7] . d[6] 0 d[5] r 7 d[4] . d[3] . d[2] r 4 d[9:2] href (row data) last byte last byte zero first byte pclk t su t hd t pclk t phh t phl t pdv first byte second byte 9665csp_ds_015 www.datasheet.co.kr datasheet pdf - http://www..net/
register table version 1.1, october 10, 2007 proprietary to omnivisi on technologies, inc. 11 o mni ision register table table 5 provides a list and description of the device control registers contained in the OV9665. for all register enable/disable bits, enable = 1 and disable = 0. the device slave addresses are 0x60 for wr ite and 0x61 for read. note: reserved registers or register bi ts may be non-functional, special function or sensitive to the sens or. please refer to omnivision?s recommended register settings. table 5 device control register list (sheet 1 of 16) address (hex) register name default (hex) r/w description 00 gain 00 rw agc gain control bit[7:0]: gain setting ? range: 1x to 32x gain = (bit[7]+1) x (bit[6]+1) x (bit [5]+1) x (bit[4]+1) x (1+bit[3:0])/16) note : set com8[2] = 0 to disable agc. 01 blue 40 rw blue gain control 02 red 40 rw blue gain control 03 com1 03 rw common control 1 bit[7:6]: dummy frame control - effective when register bit com6 [3] = 1 (0x0f) (night mode enable) 00: not used 01: allow 1 dummy frame 10: allow 3 dummy frames 11: allow 7 dummy frames bit[5:4]: reserved bit[3:2]: vertical window end line control 2 lsbs (see register vend for 8 msbs) bit[1:0]: vertical window start line control 2 lsbs (see register vstrt for 8 msbs) 04 reg04 28 rw register 04 bit[7]: horizontal mirror (effective when register bit reg33 [3] = 1 (0x33) bit[6]: vertical flip bit[5:2]: reserved bit[1:0]: aec low 2 lsbs ? aec[1:0] (see register aec for aec[9:2] and register reg45 [5:0] for aec[15:10]) 05 reg05 00 rw register 05 bit[7:3]: reserved bit[2:0]: uv adjust slope[5:3] between gain threshold 1 and gain threshold 2. for others , refer to registers com1 [5:4] (0x03) and reg60 [2:0] (0x60). www.datasheet.co.kr datasheet pdf - http://www..net/
12 proprietary to omnivisi on technologies, inc. version 1.1, october 10, 2007 OV9665 color cmos sxga (1.3 megapixel) omnipixel2? c amera c hip ? sensor o mni ision 06 reg06 10 rw register 06 bit[7:6]: dummy line insertion beginning gain 00: 2x 01: 4x 10: 8x 11: 8x bit[5:0]: reserved 07 reg07 a4 rw register 07 bit[7]: reserved bit[6:4]: vs start point bit[3]: reserved bit[2:0]: vs width 08 rsvd xx ? reserved 09 com2 00 rw common control 2 bit[7:5]: always precharge bit[4]: sleep mode enable (sccb standby enable) 0: normal mode 1: sleep mode bit[3]: pin d0 output control 0: d0 1: strobe bit[2]: reserved bit[1:0]: output drive current select 00: weakest 01: double capability 10: double capability 11: triple drive current 0a pid 96 r product id number msb (read only) 0b ver 63 r product id number lsb (read only) 0c com3 38 rw common control 3 bit[7:3]: reserved bit[2]: manually set banding 0: 60 hz 1: 50 hz bit[1]: auto set banding bit[0]: snapshot option 0: enable live video output after snapshot sequence 1: output single frame only 0d reg0d 80 rw register 0d bit[7:5]: reserved bit[4]: dsp clock selection 0: for sxga mode 1: for vga 30 mode bit[3:0]: reserved table 5 device control register list (sheet 2 of 16) address (hex) register name default (hex) r/w description www.datasheet.co.kr datasheet pdf - http://www..net/
register table version 1.1, october 10, 2007 proprietary to omnivisi on technologies, inc. 13 o mni ision 0e rsvd xx ? reserved 0f com6 46 rw common control 6 bit[7:4]: reserved bit[3]: night mode enable 0: disable 1: enable bit[2:0]: reserved 10 aec 00 rw automatic exposure control - aec[9:2] (see register reg45 [5:0] for aec[15:10] and register reg04 for aec[1:0]) aec[15:0]: exposure time tex = tline x aec[15:0] note : the maximum exposure time is 1 frame period even if tex is longer than 1 frame period 11 clkrc 80 rw clock rate control bit[7:6]: reserved bit[5:0]: clock divider for frame rate adjustment clk = xvclk / (decimal value of clkrc[5:0] + 1) 12 com7 00 rw common control 7 bit[7]: srst 1: initiates soft reset. all registers are set to factory default values after which the chip resumes normal operation bit[6:5]: resolution selection 00: sxga (full size) mode 01: not used 10: vga mode 11: not used bit[4:3]: reserved bit[2]: zoom mode bit[1:0]: reserved table 5 device control register list (sheet 3 of 16) address (hex) register name default (hex) r/w description www.datasheet.co.kr datasheet pdf - http://www..net/
14 proprietary to omnivisi on technologies, inc. version 1.1, october 10, 2007 OV9665 color cmos sxga (1.3 megapixel) omnipixel2? c amera c hip ? sensor o mni ision 13 com8 e7 rw common control 8 bit[7]: reserved bit[6]: aec step size limit bit[5]: banding filter selection 0: off 1: on, set minimum exposure to 1/120s or 1/100s bit[4:3]: reserved bit[2]: agc auto/manual control selection 0: manual 1: auto bit[1]: awb auto/manual control selection 0: manual 1: auto bit[0]: exposure control 0: manual 1: auto 14 com9 40 rw common control 9 bit[7:5]: agc gain ceiling 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x 101: not used 110: not used 111: not used bit[4]: reserved bit[3]: exposure time can be less than limitation of banding filter (1/120s or 1/100s) when light is too strong bit[2]: data output format - vsync drop option 0: vsync always exists 1: vsync will drop when frame data drops bit[1]: enable drop frame when aec step is larger than the exposure gap bit[0]: reserved 15 com10 00 rw common control 10 bit[7:6]: reserved bit[5]: pclk output selection (works on row data output) 0: pclk always output 1: pclk output qualified by href bit[4:2]: reserved bit[1]: vsync polarity 0: positive 1: negative bit[0]: reserved 16 green 40 rw green gain control table 5 device control register list (sheet 4 of 16) address (hex) register name default (hex) r/w description www.datasheet.co.kr datasheet pdf - http://www..net/
register table version 1.1, october 10, 2007 proprietary to omnivisi on technologies, inc. 15 o mni ision 17 hrefst 0d rw horizontal window start 8 msbs (3 lsbs in register reg32 [2:0]) bit[10:0]: select beginning of horizontal window, each lsb represents two pixels 18 hrefend 5d rw horizontal window end 8 msbs (3 lsbs in register reg32 [5:3]) bit[10:0]: select end of horizontal window, each lsb represents two pixels 19 vstrt 01 rw vertical window line start 8 msbs (2 lsbs are in register com1 [1:0]) bit[9:0]: select start of vertical window, each lsb represents two scan lines 1a vend 82 rw vertical window line end 8 msbs (2 lsbs are in register com1 [3:2]) bit[9:0]: select end of vertical window, each lsb represents two scan lines 1b rsvd xx ? reserved 1c midh 7f r manufacturer id byte ? high (read only = 0x7f) 1d midl a2 r manufacturer id byte ? low (read only = 0xa2) 1e reg1e f9 rw register 1e bit[7]: white defect pixel correction 0: disable 1: enable bit[6]: black defect pixel correction 0: disable 1: enable bit[5:0]: reserved 1f-23 rsvd xx ? reserved 24 aew 78 rw luminance signal high range for aec/agc operation aec/agc value decreases in auto mode when average luminance is greater than aew[7:0] 25 aeb 68 rw luminance signal low range for aec/agc operation aec/agc value increases in auto mode when average luminance is less than aeb[7:0] 26 vv d4 rw fast mode large step range thresholds (effective only in aec/agc fast mode) bit[7:4]: high threshold bit[3:0]: low threshold aec/agc may change in larger steps when luminance average is greater than vv[7:4] or less than vv[3:0] 27-29 rsvd xx ? reserved table 5 device control register list (sheet 5 of 16) address (hex) register name default (hex) r/w description www.datasheet.co.kr datasheet pdf - http://www..net/
16 proprietary to omnivisi on technologies, inc. version 1.1, october 10, 2007 OV9665 color cmos sxga (1.3 megapixel) omnipixel2? c amera c hip ? sensor o mni ision 2a reg2a 00 rw common control 2a bit[7:4]: line interval adjustment value 4 msbs (see register reg2b [7:0] for 8 msbs) bit[3:2]: hsync timing end point adjustment 2 msbs (see register hedy for 8 lsbs) bit[1:0]: hsync timing start point adjustment 2 msbs (see register hsdy for 8 lsbs) 2b reg2b 00 rw common control 2b bit[7:0]: line interval adjustment value 8 lsbs (see register reg2a [7:4] for 4 msbs) the frame rate will be adjusted by changing the line interval. each lsb will add 1/1520 tframe in sxga and 1/760 tframe in vga mode to the frame period. 2c rsvd xx ? reserved 2d addvsl 00 rw vsync pulse width 8 lsbs bit[7:0]: line periods added to vsync width. default vsync output width is 4 x tline. each lsb count will add 1 x tline to the vsync active period. 2e addvsh 00 rw vsync pulse width 8 msbs bit[7:0]: line periods added to vsync width. default vsync output width is 4 x tline. each msb count will add 256 x tline to the vsync active period. 2f yavg 00 r luminance average (this register will auto update) 30 hsdy 08 rw hsync position and width start 8 lsbs this register and register reg2a [1:0] define the hsync start position. each lsb will shift the hsync starting point by a 2 pixel period. 31 hedy 20 rw hsync position and width end 8 lsbs this register and register reg2a [3:2] define the hsync end position. each lsb will shift the hsync starting point by a 2 pixel period. 32 reg32 24 rw common control 32 bit[7:6]: pixel clock divide option 00: no effect on pclk 01: no effect on pclk 10: pclk frequency divide by 2 11: pclk frequency divide by 4 bit[5:3]: horizontal window end position 3 lsbs (8 lsbs in register hrefend ) bit[2:0]: horizontal window start position 3 lsbs (8 lsbs in register hrefst ) 33 reg33 c0 rw register 33 bit[7:4]: reserved bit[3]: mirror function (used with register bit reg04 [7] (0x04)) bit[2:0]: reserved 34-35 rsvd xx ? reserved table 5 device control register list (sheet 6 of 16) address (hex) register name default (hex) r/w description www.datasheet.co.kr datasheet pdf - http://www..net/
register table version 1.1, october 10, 2007 proprietary to omnivisi on technologies, inc. 17 o mni ision 36 reg36 94 rw register 36 bit[7:6]: reserved bit[5]: auto de-noise divider value 0: 128 1: 64 bit[4:0]: reserved 37-3a rsvd xx ? reserved 3b reg3b 00 rw power control 3b bit[7:4]: reserved bit[3]: bypass internal regulator 0: use internal regulator to generate v dd-d power 1: bypass internal regulator (v dd-d power needs to be provided by an external source) bit[2:0]: reserved 3c rsvd xx ? reserved 3d reg3d 3c rw common control 3d bit[7:6]: reserved bit[5:0]: pll divider f clk = xclk (0x40 ? reg3d[5:0]) / 8 / ( clkrc [5:0] + 1) 3e reg3e 50 rw register 3e bit[7]: pll bypass option 0: enable pll 1: bypass pll bit[6:0]: reserved 3f-40 rsvd xx ? reserved 41 reg41 00 rw register 41 bit[7:5]: uv adjust offset value[5:3] between gain threshold 1 and gain threshold 2. for others, refer to register reg5b [4:2] (0x5b). bit[4:0]: reserved 42 rsvd xx ? reserved 43 reg43 00 rw register 43 bit[7]: 9-zone average aec option 0: full size and vga30 1: other size bit[6:0]: reserved table 5 device control register list (sheet 7 of 16) address (hex) register name default (hex) r/w description www.datasheet.co.kr datasheet pdf - http://www..net/
18 proprietary to omnivisi on technologies, inc. version 1.1, october 10, 2007 OV9665 color cmos sxga (1.3 megapixel) omnipixel2? c amera c hip ? sensor o mni ision 44 reg44 00 rw register 44 bit[7]: reserved bit[6]: vertical line divider - works in scaling mode 0: no divider 1: divider bit[5:4]: reserved bit[3]: vertical line divider number - works in scaling mode 0: divide vertical line by 2 1: divide vertical line by 4 bit[2:0]: reserved 45 reg45 00 rw register 45 bit[7:6]: agc[9:8], agc highest gain control bit[5:0]: aec[15:10 ], aec 6 msbs (see register aec for aec[9:2] and register reg04 for aec[1:0]). 46 fll 00 rw frame length adjustment 8 lsbs each bit will add 1 horizontal line timing in frame 47 flh 00 rw frame length adjustment 8 msbs each bit will add 256 horizontal lines timing in frame 48-4a rsvd xx ? reserved 4b com22 00 rw common control 22 bit[7:0]: flash light control 4c-4d rsvd xx ? reserved 4e com25 05 rw common control 25 bit[7:6]: 50 hz banding aec 2 msbs bit[5:4]: 60 hz banding aec 2 msbs bit[3:0]: reserved 4f bd50 9e rw 50 hz banding aec 8 lsbs (see register com25 [7:6] for 2 msbs) 50 bd60 84 rw 60 hz banding aec 8 lsbs (see register com25 [5:4] for 2 msbs) 51-59 rsvd xx ? reserved 5a reg5a 57 rw register 5a bit[7:4]: 50 hz banding maximum aec step bit[3:0]: 60 hz banding maximum aec step 5b reg5b 20 rw register 5b bit[7:5]: reserved bit[4:2]: uv adjust offset value[5:3] between gain threshold 1 and gain threshold 2. for others, refer to register reg41 [7:5] (0x41). bit[1:0]: reserved table 5 device control register list (sheet 8 of 16) address (hex) register name default (hex) r/w description www.datasheet.co.kr datasheet pdf - http://www..net/
register table version 1.1, october 10, 2007 proprietary to omnivisi on technologies, inc. 19 o mni ision 5c reg5c 00 rw register 5c bit[7]: average aec option 0: 9-zone average aec 1: full average aec bit[6:0]: reserved 5d reg5d 55 rw 9-zone average weight option - avgsel[7:0] 5e reg5e 55 rw 9-zone average weight option - avgsel[15:8] 5f reg5f 21 rw register 5f bit[7:2]: reserved bit[1:0]: 9-zone average weight option - avgsel[17:16] 60 reg60 80 rw register 60 bit[7:3]: reserved bit[2:0]: uv adjust slope[2:0] between gain threshold 1 and gain threshold 2. for others , refer to registers com1 [5:4] (0x03) and reg05 [2:0] (0x05). 61 histo_low 80 rw histogram algorithm low level bit[7:0]: histogram algorithm low level 62 histo_high 90 rw histogram algorithm high level bit[7:0]: histogram algorithm high level 63 reg63 01 rw register 63 bit[7:6]: reserved bit[5]: raw data output format (valid when register reg07 [1:0] is 2?b11) 0: dsp function (awb and gamma) works on raw output data 1: dsp functions do not work on raw output data bit[4:0]: reserved 64 reg64 20 rw register 64 bit[7]: blc line select 0: sxga 1: other resolution bit[6:0]: reserved 65 reg65 10 rw register 65 bit[7:2]: reserved bit[1:0]: uv adjustment gain threshold 2 value[4:3] 66 reg66 00 rw register 66 bit[7:5]: uv adjustment gain threshold 2 value[2:0] bit[4:0]: reserved 67-69 rsvd xx ? reserved table 5 device control register list (sheet 9 of 16) address (hex) register name default (hex) r/w description www.datasheet.co.kr datasheet pdf - http://www..net/
20 proprietary to omnivisi on technologies, inc. version 1.1, october 10, 2007 OV9665 color cmos sxga (1.3 megapixel) omnipixel2? c amera c hip ? sensor o mni ision 6a reg6a 24 rw register 6a bit[7:5]: reserved bit[4]: fifo manual option (works with scaling function) 0: auto mode 1: manual mode bit[3:0]: reserved 6b-74 rsvd xx ? reserved 75 reg75 d0 rw histogram-based aec lower limit of probability - lph 76 reg76 d0 rw histogram-based aec upper limit of probability - upl 77 reg77 f0 rw histogram-based aec probability threshold for lrl - tpl 78 reg78 90 rw histogram-based aec probability threshold for hrl - tph 79 reg79 e5 rw register 79 bit[7:2]: high nibble of luminance thrreshold for aec/agc speed control bit[3:0]: low nibble of luminance threshold for aec/agc speed control 7a-7b rsvd xx ? reserved 7c reg7c 05 rw register 7c bit[7]: aec option 0: average-based aec 1: histogram-based aec bit[6:0]: reserved 7d reg7d 00 rw lens correction center coordinates x bit[7]: sign bit bit[6:0]: x-coordinate for lens correction center 7e reg7e 00 rw lens correction center coordinates y bit[7]: sign bit bit[6:0]: y-coordinate for lens correction center 7f reg7f 18 rw radius of the circular section where lens correction is not needed 80 reg80 04 rw lens correction blue gain parameter - this register is valid when register lc7 [2] (0x83) = 1 81 reg81 04 rw lens correction red gain parameter - this register is valid when register lc7 [2] (0x83) = 1 82 reg82 04 rw lens correction green gain parameter table 5 device control register list (sheet 10 of 16) address (hex) register name default (hex) r/w description www.datasheet.co.kr datasheet pdf - http://www..net/
register table version 1.1, october 10, 2007 proprietary to omnivisi on technologies, inc. 21 o mni ision 83 lc7 06 rw bit[7:3]: reserved bit[2]: lens correct ion control select 0: use register reg82 (0x82) for gain parameter for r, g, and b channels 1: use register reg82 (0x82) for green gain parameter, register reg80 (0x80) for blue gain parameter, and register reg81 (0x81) for red gain parameter bit[1]: reserved bit[0]: lens correction enable switch 0: disable 1: enable 84 reg84 86 rw de-noise level 85 reg85 e7 rw register 85 bit[7:5]: reserved bit[4]: raw/yuv (only works when register bits regd7 [1:0] (0xd7) = 0?b10) bit[3]: fifo enable (works with scaling function) bit[2]: gamma enable option 0: disable 1: enable bit[1]: awb gain bit[0]: awb 86-87 rsvd xx ? reserved 88 reg08 a2 rw register 88 bit[7:5]: awb option 0: advanced awb 1: simple awb bit[6:0]: reserved 89-9a rsvd xx ? reserved 9b gam1 04 rw gamma curve segment 1 end point 9c gam2 07 rw gamma curve segment 2 end point 9d gam3 10 rw gamma curve segment 3 end point 9e gam4 28 rw gamma curve segment 4 end point 9f gam5 36 rw gamma curve segment 5 end point a0 gam6 44 rw gamma curve segment 6 end point a1 gam7 52 rw gamma curve segment 7 end point a2 gam8 60 rw gamma curve segment 8 end point a3 gam9 6c rw gamma curve segment 9 end point a4 gam10 78 rw gamma curve segment 10 end point a5 gam11 8c rw gamma curve segment 11 end point table 5 device control register list (sheet 11 of 16) address (hex) register name default (hex) r/w description www.datasheet.co.kr datasheet pdf - http://www..net/
22 proprietary to omnivisi on technologies, inc. version 1.1, october 10, 2007 OV9665 color cmos sxga (1.3 megapixel) omnipixel2? c amera c hip ? sensor o mni ision a6 gam12 9e rw gamma curve segment 12 end point a7 gam13 bb rw gamma curve segment 13 end point a8 gam14 d2 rw gamma curve segment 14 end point a9 gam15 e5 rw gamma curve segment 15 end point aa slop 24 rw gamma curve segment 15 slope ab regab e7 rw register ab bit[7:4]: reserved bit[3]: scaling enable option 0: disable 1: enable bit[2]: sharpness enable option 0: disable 1: enable bit[1]: de-noise enable option 0: disable 1: enable bit[0]: reserved ac regac 02 rw de-noise offset limit in auto de-noise mode ad regad 25 rw register ad bit[7:5]: reserved bit[4:0]: sharpness value when gain < 2x ae regae 20 rw register ae bit[7:3]: reserved bit[2]: sharpness threshold double bit[1:0]: reserved af rsvd xx ? reserved b0 regb0 43 rw register b0 bit[7]: manual de-noise mode enable 0: auto de-noise mode 1: manual de-noise bit[6:0]: reserved b1-b6 rsvd xx ? reserved b7 regb7 00 rw register b7 bit[7]: scaling mode vertical output size bit[0] (11 bits total). for others, refer to registers regb8 [7:6] and regbc bit[6:4]: scaling mode horizontal output size bit[2:1] (11 bits total). for others, refer to register regbb bit[3:0]: reserved table 5 device control register list (sheet 12 of 16) address (hex) register name default (hex) r/w description www.datasheet.co.kr datasheet pdf - http://www..net/
register table version 1.1, october 10, 2007 proprietary to omnivisi on technologies, inc. 23 o mni ision b8 regb8 00 rw register b8 bit[7:6]: scaling mode vertical output size bit[2:1] (11 bits total). for others, refer to registers regb7 [7] and regbc bit[5:3]: scaling mode vertical inpu t size bit[2:0] (11 bits total). for others, refer to register regba bit[2:0]: scaling mode horizontal inpu t size bit[2:0] (11 bits total). for others, refer to register regb9 b9 regb9 a0 rw scaling mode horizontal input size bit[10:3] (11 bits total). for others, refer to register regb8 [2:0] ba regba 80 rw scaling mode vertical input size bi t[10:3] (11 bits total). for others, refer to register regb8 [5:3] bb regbb a0 rw scaling mode horizontal output size [10:3] (11 bits total). for others, refer to registers regb8 [7:6] and regb7 [6:4] bc regbc 80 rw scaling mode vertical output size[10: 3] (11 bits total). for others refer to registers regb7 [7] and regb8 [7:6] bd cmx1 05 rw color matrix parameter 1 y = ( cmx1 r + cmx2 g + cmx3 b) / 32 be cmx2 16 rw color matrix parameter 2 bf cmx3 05 rw color matrix parameter 3 c0 cmx4 07 rw color matrix parameter 4 u = ( cmx4 r + cmx5 g + cmx6 b) / 32 c1 cmx5 18 rw color matrix parameter 5 c2 cmx6 1f rw color matrix parameter 6 c3 cmx7 2b rw color matrix parameter 7 v = ( cmx7 r + cmx8 g + cmx9 b) / 32 c4 cmx8 2b rw color matrix parameter 8 c5 cmx9 00 rw color matrix parameter 9 c6 cmx10 98 rw color matrix control 1 bit[7]: sign bit of cmx8 bit[6]: sign bit of cmx7 bit[5]: sign bit of cmx6 bit[4]: sign bit of cmx5 bit[3]: sign bit of cmx4 bit[2]: sign bit of cmx3 bit[1]: sign bit of cmx2 bit[0]: sign bit of cmx1 table 5 device control register list (sheet 13 of 16) address (hex) register name default (hex) r/w description www.datasheet.co.kr datasheet pdf - http://www..net/
24 proprietary to omnivisi on technologies, inc. version 1.1, october 10, 2007 OV9665 color cmos sxga (1.3 megapixel) omnipixel2? c amera c hip ? sensor o mni ision c7 cmx11 10 rw color matrix control 2 bit[7]: sign bit of cmx9 bit[6]: reserved bit[5]: auto uv adjustment enable 0: disable 1: enable bit[4]: special digital effects (sde) enable 0: disable 1: enable bit[3:0]: reserved c8 regc8 02 rw register c8 bit[7]: fixed y output value 0: disable 1: enable bit[6]: negative output 0: disable 1: enable bit[5]: gray scale output 0: disable 1: enable bit[4]: fixed v output value 0: disable 1: enable bit[3]: fixed u output value 0: disable 1: enable bit[2]: contrast function enable 0: disable 1: enable bit[1]: color saturation function enable 0: disable 1: enable bit[0]: hue adjustment enable 0: disable 1: enable c9 regc9 80 rw hue adjustment cosine parameter ca regca 00 rw hue adjustment sine parameter cb regcb 40 rw saturation u gain value cc regcc 40 rw saturation v gain value cd regcd 80 rw fixed u output value ce regce 80 rw fixed v output value table 5 device control register list (sheet 14 of 16) address (hex) register name default (hex) r/w description www.datasheet.co.kr datasheet pdf - http://www..net/
register table version 1.1, october 10, 2007 proprietary to omnivisi on technologies, inc. 25 o mni ision cf regcf 00 rw y offset value y? = [(y + yoffset) ygain] + ybrightness when enabling contrast function d0 regd0 20 rw y gain value d1 regd1 00 rw y brightness value d2 regd2 00 rw register d2 bit[7]: auto uv adjustment enable bit[6:5]: reserved bit[4:0]: uv adjust offset value after gain threshold 2 d3 regd3 00 rw fifo delay timing configuration (works with scaling function) d4 rsvd xx ? reserved d5 regd5 00 rw io pad direction control bit[7]: d7 direction control 0: input 1: output bit[6]: d6 direction control 0: input 1: output bit[5]: d5 direction control 0: input 1: output bit[4]: d4 direction control 0: input 1: output bit[3]: d3 direction control 0: input 1: output bit[2]: d2 direction control 0: input 1: output bit[1]: d1 direction control 0: input 1: output bit[0]: d0 direction control 0: input 1: output d6 regd6 00 rw register d6 bit[7:2]: reserved bit[1]: d9 direction control 0: input 1: output bit[0]: d8 direction control 0: input 1: output table 5 device control register list (sheet 15 of 16) address (hex) register name default (hex) r/w description www.datasheet.co.kr datasheet pdf - http://www..net/
26 proprietary to omnivisi on technologies, inc. version 1.1, october 10, 2007 OV9665 color cmos sxga (1.3 megapixel) omnipixel2? c amera c hip ? sensor o mni ision d7 regd7 10 rw register d7 bit[7:5]: reserved bit[4]: yu swap function 0: u y v y 1: y u y v bit[3]: data pins swap function (changes msb to d0 and lsb to d9) - works in yuv mode 0: disable 1: enable bit[2]: href to hsync 0: output href signal 1: output hsync signal bit[1:0]: data output format selection 00: yuv output 01: rgb output 10: isp raw output 11: raw output d8 regd8 c4 rw register d8 bit[7:6]: reserved bit[5]: href/hsync negative output 0: positive output 1: negative output bit[4]: reserved bit[3]: ccir656 output selection 0: disable 1: enable bit[2]: reserved bit[1:0]: rgb data output format selection (effective when register bits regd7 [1:0] = 01) 00: not used 01: rgb565 10: rgb555 11: rgb444 d9 regd9 64 rw register d9 bit[7:4]: sharpness value when 4x < gain < 8x bit[3:0]: sharpness value when 2x < gain < 4x da regda 86 rw register da bit[7:4]: sharpness value when 16x < gain bit[3:0]: sharpness value when 8x < gain < 16x db-de rsvd xx ? reserved note: all other registers are factory-reserved. please contac t omnivision technologies for reference register settings. table 5 device control register list (sheet 16 of 16) address (hex) register name default (hex) r/w description www.datasheet.co.kr datasheet pdf - http://www..net/
package specifications version 1.1, october 10, 2007 proprietary to omnivisi on technologies, inc. 27 o mni ision package specifications the OV9665 uses a 26-pin chip scale package 2 (csp2). refer to figure 11 for package information, ta b l e 6 for package dimensions and figure 12 for the array center on the chip. figure 11 OV9665 package specifications note: for ovt devices that are lead-fr ee, all part marking letters are lower case. underlining the last digit of the lot number indicates csp2 is used. table 6 csp package dimensions parameter symbol min nominal max unit package body dimension x a 4460 4485 4510 m package body dimension y b 4960 4985 5010 m package height c 845 905 965 m ball height c1 150 180 210 m package body thickness c2 680 725 770 m cover glass thickness c3 375 400 425 m airgap between cover glass and sensor c4 30 45 60 m ball diameter d 320 350 380 m total pin count n 26 pin count x-axis n1 5 pin count y-axis n2 6 pins pitch x-axis j1 660 m pins pitch y-axis j2 660 m edge-to-pin center distance analog x s1 893 923 953 m edge-to-pin center distance analog y s2 813 843 873 m 1 2 3 4 5 5 4 3 2 1 a b c d e f a a b c d e f a b c d e 660 660 j1 s1 center of bga (die) = center of the package b 350 j2 c2 c1 glass die c c3 c4 s2 bottom view (bumps up) top view (bumps down) side view 9665csp_ds_016 www.datasheet.co.kr datasheet pdf - http://www..net/
28 proprietary to omnivisi on technologies, inc. version 1.1, october 10, 2007 OV9665 color cmos sxga (1.3 megapixel) omnipixel2? c amera c hip ? sensor o mni ision sensor array center figure 12 OV9665 sensor array center note1 this drawing is not to scale and is for reference only. note2 as most optical assemblies invert and mirror the image, the chip is typically mounted with pin a1 oriented down on the pcb. OV9665 a1 a2 a3 a4 a5 2608 m 2072 m sensor array array center (1.0 m, 146.7 m) scan origin (1305.0 m, 1182.7 m) die center (0 m, 0 m) top view 9665csp_ds_012 www.datasheet.co.kr datasheet pdf - http://www..net/
package specifications version 1.1, october 10, 2007 proprietary to omnivisi on technologies, inc. 29 o mni ision chief ray angle figure 13 OV9665 chief ray angle image height (mm) angle() 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1.8 0 30 25 20 15 10 5 chief ray angle 9665csp_ds_013 www.datasheet.co.kr datasheet pdf - http://www..net/
30 proprietary to omnivisi on technologies, inc. version 1.1, october 10, 2007 OV9665 color cmos sxga (1.3 megapixel) omnipixel2? c amera c hip ? sensor o mni ision ir reflow ramp rate requirements OV9665 lead-free packaged devices figure 14 ir reflow ramp rate requirements note: for ovt devices that are lead-fr ee, all part marking letters are lower case. table 7 reflow conditions condition exposure average ramp-up rate (30c to 217c) less than 3c per second > 100c between 330 - 600 seconds > 150c at least 210 seconds > 217c at least 30 seconds (30 ~ 120 seconds) peak temperature 245c cool-down rate (peak to 50c) less than 6c per second time from 30c to 245c no greater than 390 seconds time (sec) temperature (c) -22 -2 18 38 58 78 98 118 138 158 178 358 338 318 298 278 258 238 218 198 369 0.0 300.0 280.0 220.0 240.0 260.0 200.0 180.0 140.0 160.0 120.0 100.0 80.0 60.0 40.0 20.0 z1 z2 z3 z4 z5 z6 z7 end 9665csp_ds_014 www.datasheet.co.kr datasheet pdf - http://www..net/
package specifications version 1.1, october 10, 2007 proprietary to omnivisi on technologies, inc. 31 o mni ision note : ? all information shown herein is current as of the revision and publication date. please refer to the omnivision web site (http://www.ovt.com ) to obtain the current versions of all documentation. ? omnivision technologies, inc. reserves the ri ght to make changes to their products or to discontinue any product or service without further notice (it is advisable to obtain current product documentation prior to placing orders). ? reproduction of information in omnivision product documentation and specifications is permissible only if reproduction is without alte ration and is accompanied by all associated warranties, conditions, li mitations and notices. in such cases, omnivision is not responsible or liable for any information reproduced. ? this document is provided with no warrant ies whatsoever, including any warranty of merchantability, non-infringement, fitness fo r any particular purpose, or any warranty otherwise arising out of any proposal, specifi cation or sample. furthermore, omnivision technologies, inc. disclaims all li ability, including liability for in fringement of any proprietary rights, relating to use of information in this document. no license, expressed or implied, by estoppels or otherwise, to any intellec tual property rights is granted herein. ? ?omnivision?, ?variopixel? and the omnivision logo are registered trademarks of omnivision technologies, inc. ?omnipixel2? and ?camerac hip? are trademarks of omnivision technologies, inc. all other trade, product or service names refe renced in this release may be trademarks or registered trademarks of thei r respective holders. third-party brands, names, and trademarks are the property of their respective owners. for further information, please feel free to contact omnivision at info@ovt.com . omnivision technologies, inc. 1341 orleans drive sunnyvale, ca usa (408) 542-3000 www.datasheet.co.kr datasheet pdf - http://www..net/
32 proprietary to omnivisi on technologies, inc. version 1.1, october 10, 2007 OV9665 color cmos sxga (1.3 megapixel) omnipixel2? c amera c hip ? sensor o mni ision www.datasheet.co.kr datasheet pdf - http://www..net/
o mni tm ision r evision c hange l ist document title: OV9665 (csp2) datasheet version: 1.0 d escription of c hanges ? initial release www.datasheet.co.kr datasheet pdf - http://www..net/
o mni tm ision r evision c hange l ist document title: OV9665 (csp2) datasheet version: 1.1 d escription of c hanges the following changes were made to version 1.0: ? in figure 6 on page 7, changed timing between falling edge of href and rising edge of vsync from 13716 tp to 15223 tp ? in figure 7 on page 7, changed timing between falling edge of href and rising edge of vsync from 13679 tp to 13697 tp ? in table 5 on page 12, changed register name, default value, and r/w type of register 0x0d from ?rsvd?, ?xx?, and ??? to ?r eg0d?, ?80?, and ?rw?, respectively ? in table 5 on page 12, changed description of register 0x0d from ?reserved? to: register 0d bit[7:5]: reserved bit[4]: dsp clock selection 0: for sxga mode 1: for vga 30 mode bit[3:0]: reserved www.datasheet.co.kr datasheet pdf - http://www..net/

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